/**************************************************************************//**
 * @file     pri_rf.c
 * @version  V1.00
 * $Date: 20/12/14 9:39a $
 * @brief    Panchip private rf driver source file
 *
 * @note
 * Copyright (C) 2020 Panchip Technology Corp. All rights reserved.
 *****************************************************************************/
 
#include "PanSeries.h"


#if 0

/**
  * @brief  This function used to set private rf payload lenth
  * @param  rf: where rf is a private rf peripheral base address 
  * @param  mode: tx or rx mode select,including:
  * 							PRI_RF_MODE_SEL_TX
  * 							PRI_RF_MODE_SEL_RX
  * @param  len: payload lenth 
  * @retval none
  */ 
void PRI_RF_SetTrxPayloadLen(PRI_RF_T *rf,uint8_t mode,uint8_t len)
{
	if(mode == PRI_RF_MODE_SEL_TX) {
		PRI_RF_WRITE_REG_VALUE(rf,R00_CTL,TX_PAYLOAD_LEN,len);
	}else {
		PRI_RF_WRITE_REG_VALUE(rf,R00_CTL,RX_PAYLOAD_LEN,len);
	}
}

/**
  * @brief  This function used to set private rf address byte lenth
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  len: address byte lenth ,including:
  *  						PRI_RF_ADDR_BYTE_LEN_INVALID			
  *  						PRI_RF_ADDR_BYTE_LEN_3		
  *  						PRI_RF_ADDR_BYTE_LEN_4		
  *  						PRI_RF_ADDR_BYTE_LEN_5		
  * @retval true value valid
  * @retval false value invalid
  */ 
bool PRI_RF_SetAddrByteLen(PRI_RF_T *rf,uint8_t len)
{
    if(PRI_RF_ADDR_BYTE_LEN_INVALID == len) {
		return false;
	}
	
	PRI_RF_WRITE_REG_VALUE(rf,R00_CTL,ADDR_BYTE_LEN,len);
	return true;
}



/**
  * @brief  This function used to set pid manual
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  pid: pid value
  * @retval none
  */ 
void PRI_RF_SetPidManualEn(PRI_RF_T *rf,uint8_t pid)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R01_INT_CTL,TX_PID_MANUAL_EN,ENABLE);
	PRI_RF_WRITE_REG_VALUE(rf,R01_INT_CTL,TX_PID_MANUAL,pid);
}

/**
  * @brief  This function used to set rx wait time 
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  NewState: new state of enabling state
  * @retval none
  */ 
void PRI_RF_SetRxWaitTime(PRI_RF_T *rf,uint16_t time)
{
  if(time > 0) {
    PRI_RF_SET_FUNC_ENABLE(rf,R02_TMR_CTL,RX_WAIT_TIME_EN,ENABLE);
	  PRI_RF_WRITE_REG_VALUE(rf,R02_TMR_CTL,RX_WAIT_TIME,time);
  }
}

/**
  * @brief  This function used to set private rf tx or rx address
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  mode: tx or rx mode select,including:
  * 							PRI_RF_MODE_SEL_TX
  * 							PRI_RF_MODE_SEL_RX
  * 							PRI_RF_MODE_SEL_TRX
  * @param  addr: addr base address 
  * @retval none
  */ 
void PRI_RF_SetTrxAddr(PRI_RF_T *rf,uint8_t mode,uint32_t *addr)
{
	if(mode == PRI_RF_MODE_SEL_TX) {
		PRI_RF_WRITE_REG_VALUE(rf,R05_TX_ADDR_L,L32B,*addr);
		addr++;
		PRI_RF_WRITE_REG_VALUE(rf,R06_TX_ADDR_M,M32B,*addr);
	}else if(mode == PRI_RF_MODE_SEL_RX){
		PRI_RF_WRITE_REG_VALUE(rf,R03_RX_ADDR_L,L32B,*addr);
		addr++;
		PRI_RF_WRITE_REG_VALUE(rf,R04_RX_ADDR_M,M32B,*addr);	
	} else {
		PRI_RF_WRITE_REG_VALUE(rf,R03_RX_ADDR_L,L32B,*addr);
		PRI_RF_WRITE_REG_VALUE(rf,R05_TX_ADDR_L,L32B,*addr);
		addr++;
		PRI_RF_WRITE_REG_VALUE(rf,R04_RX_ADDR_M,M32B,*addr);
		PRI_RF_WRITE_REG_VALUE(rf,R06_TX_ADDR_M,M32B,*addr);
	}
}

/**
  * @brief  This function used to set private rf tx or rx ram start address
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  mode: tx or rx mode select,including:
  * 							PRI_RF_MODE_SEL_TX
  * 							PRI_RF_MODE_SEL_RX
  * 							PRI_RF_MODE_SEL_TRX
  * @param  addr: addr base address 
  * @retval none
  */ 
void PRI_RF_SetTrxRamStartAddr(PRI_RF_T *rf,uint8_t mode,uint32_t addr)
{
	if(mode == PRI_RF_MODE_SEL_TX) {
		PRI_RF_WRITE_REG_VALUE(rf,R07_SRAM_CTL,TX_START_ADDR,addr);
	}else {
		PRI_RF_WRITE_REG_VALUE(rf,R07_SRAM_CTL,RX_START_ADDR,addr);
	}
}

/**
  * @brief  This function used to adjust private rf tx or rx ram state is ready or not
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  mode: tx or rx mode select,including:
  * 							PRI_RF_MODE_SEL_TX
  * 							PRI_RF_MODE_SEL_RX
  * 							PRI_RF_MODE_SEL_TRX
  * @retval true ram is ready
  * @retval false ram is not ready
  */ 
bool PRI_RF_IsTrxRamReady(PRI_RF_T *rf,uint8_t mode)
{
	if(mode == PRI_RF_MODE_SEL_TX) {
		return (rf->R07_SRAM_CTL & R07_SRAM_CTL_TX_READY_Msk)?(false):(true);
	}else {
		return (rf->R07_SRAM_CTL & R07_SRAM_CTL_RX_READY_Msk)?(false):(true);
	}
}
/**
  * @brief  This function used to set private rf ram ready state
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  mode: tx or rx mode select,including:
  * 							PRI_RF_MODE_SEL_TX
  * 							PRI_RF_MODE_SEL_RX
  * 							PRI_RF_MODE_SEL_TRX
  * @param  ready: ready state 
  * @retval none
  */ 
void PRI_RF_SetTrxRamReady(PRI_RF_T *rf,uint8_t mode,uint8_t ready)
{
	if(mode == PRI_RF_MODE_SEL_TRX) {
		if(ready) {
			PRI_RF_SET_FUNC_ENABLE(rf,R07_SRAM_CTL,TX_READY,ENABLE);
			PRI_RF_SET_FUNC_ENABLE(rf,R07_SRAM_CTL,RX_READY,ENABLE);
		} else {
			PRI_RF_SET_FUNC_ENABLE(rf,R07_SRAM_CTL,TX_READY,DISABLE);
			PRI_RF_SET_FUNC_ENABLE(rf,R07_SRAM_CTL,RX_READY,DISABLE);		
		}
	}
	else if(mode == PRI_RF_MODE_SEL_TX) {
		(ready)?(PRI_RF_SET_FUNC_ENABLE(rf,R07_SRAM_CTL,TX_READY,ENABLE)):(PRI_RF_SET_FUNC_ENABLE(rf,R07_SRAM_CTL,TX_READY,DISABLE));
	}else {
		(ready)?(PRI_RF_SET_FUNC_ENABLE(rf,R07_SRAM_CTL,RX_READY,ENABLE)):(PRI_RF_SET_FUNC_ENABLE(rf,R07_SRAM_CTL,RX_READY,DISABLE));
	}
}
/*** (C) COPYRIGHT 2020 Panchip Technology Corp. ***/
#endif
